1. Field of the Invention
The present invention relates to design layout preparing method and system for preparing a design pattern of a semiconductor integrated circuit.
2. Description of the Related Art
Recently, the technique of manufacturing semiconductor devices has remarkably advanced, and semiconductor devices having a minimum process dimension of 0.13 μm are mass-produced. The scale-down described above is realized by the great development of micro-pattern forming techniques such as mask-process techniques, photolithography techniques and etching techniques.
In the large pattern size generation, an LSI pattern to be formed on a wafer is intactly used as a design pattern, and a mask pattern faithful to the design pattern is produced. The mask pattern is transferred onto the wafer using a projection optical system, thereby forming a pattern approximately equal to the design pattern on the wafer.
However, the scale-down of the pattern advances; for this reason, it is difficult to faithfully form a pattern in individual processes. As a result, a problem arises such that the final processed pattern shape is not provided as the design pattern.
In order to overcome the foregoing problem, so-called mask data processing is very important. More specifically, a mask pattern different from the design pattern is produced so that the final processed pattern dimensions become approximately equal to the design pattern.
The mask data processing includes the following processings. One is MDP processing of modifying the mask pattern using graphical operation and a design rule checker (D.R.C.). Another is optical proximity correction (OPC) for correcting the optical proximity effect (OPE). The foregoing processings are made, and thereby, the mask pattern is properly corrected so that the final processed pattern dimensions are provided as desired dimensions.
In recent years, a k1 value (k1=W/(NA/λ)) becomes smaller and smaller in the lithography process with the scale-down of device patterns. (In the foregoing equation, W: design pattern dimension, λ: exposure wavelength of exposure system, and NA: numerical aperture of a lens used for the exposure system.) As a result, there is a tendency for the influence by the OPE to increase. For this reason, a very heavy load is given to the OPC.
In order to achieve high accuracy of the OPC, a model-based OPC is mainly employed. According to the model-based OPC, a proper correction value for each mask pattern is calculated using a light intensity simulator capable of accurately predicting the OPE. With a decrease of the k1 value, a design rule (DR) closely relating with the OPC becomes complicated; for this reason, the layout securing method using the DR is liable to collapse.
Recently, a new system (called Design for Manufactubility: DfM) for securing the layout is required, and various proposals to realize the new system have been made. For example, there has been proposed a layout preparing and securing method using the following system (e.g., JPN. PAT. APPLN. KOKAI Publication No. 2002-26126 and No. 2003-303742). The system is composed of a compaction tool, OPC tool, lithography simulator and dangerous pattern (a pattern having a small process margin) analysis tool.
However, even if the foregoing method is employed, it is difficult to obtain the optimum layout having a minimum layout area without dangerous patterns.
As described above, the k1 value decreases in the lithography process, and thereby, layout securement using the design rule is collapsing. In addition, a new system (DfM) for securing the layout has been proposed. However, even if the proposed new system is used, it is difficult to obtain the optimum layout having a minimum layout area without dangerous patterns.